A new approach to enhance the accuracy of selective harmonics-elimination technique for digital controllers

[1] Y. Zhang, Z. Zhao, T. Lu, Y. Zhang, and L. Yuan, “A Novel Control Scheme for Three-Level NPC Back-to-Back Converter”, 2008 IEEE Vehicle Power Propulsion Conference, pp. 1–5, September 2008.Search in Google Scholar

[2] J. I. Leon, S. Kouro, L. G. Franquelo, J. Rodriguez, and B. Wu, “The Essential Role the Continuous Evolution of Modulation Techniques for Voltage-Source Inverters in the Past, Present”, IEEE Transactions on Industrial Electronics, vol. 63, pp. 2688–2701, 2016.10.1109/TIE.2016.2519321Search in Google Scholar

[3] M. S. A. Dahidah, G. Konstantinou, and V. G. Agelidis, “A Review of Multilevel Selective Harmonic Elimination PWM: Formulations, Solving Algorithms”, IEEE Transactions on Power Electronics, vol. 30, pp. 4091–4106, 2015.10.1109/TPEL.2014.2355226Search in Google Scholar

[4] F. G. Turnbull, “Selected Harmonic Reduction in Static dc-ac Inverters”, IEEE Trans. Communication and Electronics, vol. 83, pp. 374–378, 1964.10.1109/TCOME.1964.6541241Search in Google Scholar

[5] H. S. Patel and R. G. Hoft, “Generalized Techniques of Harmonic Elimination Voltage Control in Thyristor Inverters: Part I–Harmonic Elimination”, IEEE Trans. on Ind, Appl., vol. IA-9, pp. 310–317, 1973.10.1109/TIA.1973.349908Search in Google Scholar

[6] B. Wu, S. B. Dewan, and G. R. Slemon, “PWM-CSI Inverter for Induction Motor Drives”, in Conference Record of the IEEE Industry Applications Society Annual Meeting 1989, pp, 508–513, vol. 1.Search in Google Scholar

[7] M. S. A. Dahidah and V. G. Agelidis, “Selective Harmonic Elimination PWM Control for Cascaded Multilevel Voltage Source Converters: A Generalized Formula”, IEEE Transactions on Power Electronics, vol. 23, pp. 1620–1630, 2008.10.1109/TPEL.2008.925179Search in Google Scholar

[8] S. Kundu, S. Bhowmick, and S. Banerjee, “Improvement of Power Utilisation Capability for a Three-Phase Seven-Level CHB Inverter using an Improved Selective Harmonic Elimination PWM Scheme by Sharing a Desired Proportion of Power Among the H-Bridge Cells”, in IET Power Electronics, vol. 12, no. 12, pp. 3242–3253, 16.10.2019.10.1049/iet-pel.2018.5076Search in Google Scholar

[9] M. A. Hosseinzadeh, M. Sarbanzadeh, Y. Salgueiro, M. Rivera, and P. Wheeler, “Selective Harmonic Elimination In Cascaded H-Bridge Multilevel Inverter Using Genetic Algorithm Approach”, 2019 IEEE International Conference on Industrial Technology (ICIT) Melbourne, Australia, 2019, pp. 1527–1532.10.1109/ICIT.2019.8755089Search in Google Scholar

[10] A. Moeini, H. Iman-Eini, and M. Bakhshizadeh, “Selective Harmonic Mitigation-Pulse-Width Modulation Technique with Variable DC-Link Voltages in Single Three-Phase Cascaded H-Bridge Inverters”, IET Power Electronics, vol. 7, pp. 924–932, 2014.10.1049/iet-pel.2013.0315Search in Google Scholar

[11] F. H. Dupont, J. R. Pinheiro, V. F. Montagner, and H. Pinheiro, “GA Optimization to Mitigate Voltage Harmonics of Cascade Multilevel Converters”, in 2015 CHILEAN Conference on Electrical Electronics Engineering, Information Communication Technologies (CHILECON) 2015, pp. 461–466.10.1109/Chilecon.2015.7400418Search in Google Scholar

[12] Y. Sinha and A. Nampally, “Modular Multilevel Converter Modulation using Fundamental Switching Selective Harmonic Elimination Method”, 2016 IEEE International Conference on Renewable Energy Research Applications (ICRERA), pp. 736–741, 20–23 November 2016.10.1109/ICRERA.2016.7884431Search in Google Scholar

[13] A. Perez-Basante, S. Ceballos, G. Konstantinou, J. Pou, J. Andreu, and I. M. De Alegria, “(2N+1) Selective Harmonic Elimination-PWM for Modular Multilevel Converters: A Generalized Formulation and A Circulating Current Control Method”, IEEE Transactions on Power Electronics, vol. 33, pp. 802–818, 2018.10.1109/TPEL.2017.2666847Search in Google Scholar

[14] A. Sharma, D. Singh, and S. Gao, “Harmonic Elimination in Three Phase Cascaded Multilevel Inverter using Genetic Algorithm”, 2019 IEEE International Conference on Sustainable Energy Technologies Systems (ICSETS) Bhubaneswar, India, 2019,, pp. 213–218.10.1109/ICSETS.2019.8745125Search in Google Scholar

[15] K. S. Neralwar, P. M. Meshram, and V. Borghate, “GA Based Hybrid Selective Harmonic Elimination (SHE) Technique Applied to Five-Level Nested Neutral Point Clamped (NNPC) Converter”, 2016 IEEE 1st International Conference on Power Electronics Intelligent Control Energy Systems (ICPEICES), Delhi, 2016, pp. 1–6.10.1109/ICPEICES.2016.7853430Search in Google Scholar

[16] S. R. Pulikanti, M. S. A. Dahidah, and V. G. Agelidis, “Voltage Balancing Control of Three-Level Active NPC Converter Using SHE-PWM”, IEEE Trans. Power Del., vol. 26, pp. 258–267, 2011.10.1109/TPWRD.2010.2063718Search in Google Scholar

[17] T. Kato, “Sequential Homotopy-Based Computation of Multiple Solutions for Selected Harmonic Elimination in PWM Inverters”, IEEE Transactions on Circuits Systems I: Fundamental Theory Applications, vol. 46, pp. 586–593, 1999.10.1109/81.762924Search in Google Scholar

[18] E. H. E. Aboadla, S. Khan, M. H. Habaebi, T. Gunawan, B. A. Hamidah, and M. Tohtayong, “Selective Harmonics Elimination Technique in Single Phase Unipolar H-Bridge Inverter”, 2016 IEEE Student Conference on Research Development (SCOReD), pp. 1–4, 13–14 December 2016.10.1109/SCORED.2016.7810057Search in Google Scholar

[19] A. Routray, R. Kumar Singh, and R. Mahanty, “Harmonic Minimization in Three-Phase Hybrid Cascaded Multilevel Inverter using Modified Particle Swarm Optimization”, in IEEE Transactions on Industrial Informatics, vol. 15, no. 8, pp. 4407–4417, August 2019.10.1109/TII.2018.2883050Search in Google Scholar

[20] P. Kumar Kar, A. Priyadarshi, and S. Bhaskar Karanki, “Selective Harmonics Elimination using Whale Optimisation Algorithm for a Single-Phase-Modified Source Switched Multilevel Inverter”, in IET Power Electronics, vol. 12, no. 8, pp. 1952–1963, 10.7.2019.10.1049/iet-pel.2019.0087Search in Google Scholar

[21] J. Hao, G. Zhang, Y. Zheng, W. Hu, and K. Yang, “Solution for Selective Harmonic Elimination in Asymmetric Multilevel Inverter Based on Stochastic Configuration Network Levenberg-Marquardt Algorithm”, 2019 IEEE Applied Power Electronics Conference Exposition (APEC) Anaheim, CA, USA, 2019,, pp. 2855–2858.10.1109/APEC.2019.8722057Search in Google Scholar

[22] M. Ahmed et al, “General Mathematical Solution for Selective Harmonic Elimination”, in IEEE Journal of Emerging Selected Topics in Power Electronics, 2019.Search in Google Scholar

[23] K. Yang, J. Hao, and Y. Wang, “Switching Angles Geneation for Selective Harmonic Elimination by using Artificial Neural Networks Quasi-Newton Algorithm”, 2016 IEEE Energy Conversion Congress Exposition (ECCE) pp, 1–5, 18–22 Sep 2016.10.1109/ECCE.2016.7855483Search in Google Scholar

[24] S. Mohammadalizadeh and M. Ghayeni, “A New Strategy in Selective Harmonic Elimination for a Photovoltaic Multilevel Inverter”, 2016 Iranian Conference on Renewable Energy & Distributed Generation (ICREDG), pp. 50–55, 2–3 April 2016.10.1109/ICREDG.2016.7875918Search in Google Scholar

[25] B. Ozpineci, L. M. Tolbert, and J. N. Chiasson, “Harmonic Optimization of Multilevel Converters using Genetic Algorithms”, IEEE Power Electronics Letters, vol. 3, pp. 92–95, 2005.10.1109/LPEL.2005.856713Search in Google Scholar

[26] K. L. Shi and L. Hui, “Optimized PWM Strategy Based on Genetic Algorithms”, IEEE Trans, Ind, Electron, vol. 52, pp. 1458–1461, 2005.10.1109/TIE.2005.855649Search in Google Scholar

[27] S. Ramkumar, V. Kamaraj, and S. Thamizharasan, “GA Based Optimization Critical Evaluation SHE Methods for Three-Level Inverter”, in 2011 1st International Conference on Electrical Energy Systems 2011, pp. 115–121.10.1109/ICEES.2011.5725313Search in Google Scholar

[28] S. Debnath and R. N. Ray, “Harmonic Elimination in Multilevel Inverter using GA PSO: A Comparison”, in Electrical Electronics Computer Science (SCEECS), 2012 IEEE Students’ Conference on, 2012,, pp. 1–5.10.1109/SCEECS.2012.6184789Search in Google Scholar

[29] Y. Qingguang, S. Qiang, L. Wenhua, and L. Yongqiang, “DSP LF2407 in NPC Three-Level Inverter using Constant V/f principle SHE-PWM method”, in 6th International Conference on Signal Processing 2002, pp, 1723–1726, vol. 2.Search in Google Scholar

[30] J. R. Tibola, H. Pinheiro, and R. F. D. Camargo, “Closed Loop Selective Harmonic Elimination Applied to a Grid Connected PWM Converter with LCL Filter”, XI Brazilian Power Electronics Conference pp, 746–752, 11–15 Sept, 2011.10.1109/COBEP.2011.6085282Search in Google Scholar

[31] K. Yang et al, “Real-Time Switching Angle Computation for Selective Harmonic Control”, in IEEE Transactions on Power Electronics, vol. 34, no. 8, pp. 8201–8212, Aug 2019.10.1109/TPEL.2018.2881448Search in Google Scholar

[32] M. Ahmed, A. Sheir, and M. Orabi, “Real-Time Solution Implementation of Selective Harmonic Elimination of Seven-Level Multilevel Inverter”, in IEEE Journal of Emerging Selected Topics in Power Electronics, vol. 5, no. 4, pp. 1700–1709, Dec 2017.10.1109/JESTPE.2017.2746760Search in Google Scholar

[33] V. Castiglia, R. Miceli, G. Schettino, M. G. Cimoroni, C. Buccella, and C. Cecati, “Selective Harmonic Elimination in a 5-Level Single Phase Converter with FPGA Based Controller”, 2018 5th International Symposium on Environment-Friendly Energies Applications (EFEA) Rome, 2018, pp. 1–6.10.1109/EFEA.2018.8617082Search in Google Scholar

[34] S. Ahmad, Z. A. Ganie, I. Ashraf, and A. Iqbal, “Harmonics Minimization in 3-Level Inverter Waveform its FPGA Realization”, 2018 3rd International Innovative Applications of Computational Intelligence on Power Energy Controls with their Impact on Humanity (CIPECH), Ghaziabad, India, 2018, pp. 1–5.10.1109/CIPECH.2018.8724136Search in Google Scholar

[35] Y. Zhang, Y. W. Li, N. R. Zargari, and Z. Cheng, “Improved Selective Harmonics Elimination Scheme With Online Harmonic Compensation for High-Power PWM Converters”, IEEE Trans, Ind, Electron, vol. 30, pp. 3508–3517, 2015.10.1109/TPEL.2014.2345051Search in Google Scholar

[36] M. Mitchell “An Introduction to Genetic Algorithms”, MIT Press, 1998.10.7551/mitpress/3927.001.0001Search in Google Scholar

[37] IEC 61000-2-4-2002 “Electromagnetic compatibility”, (EMC) - Part 2, Environment-Section 4, Compatibility Levels in Industrial Plants for Low-Frequency Conducted Disturbances STANDARDS, 2002.Search in Google Scholar