About this article
Published Online: Dec 31, 2020
Page range: 1 - 14
Received: Jun 14, 2020
Accepted: Sep 01, 2020
DOI: https://doi.org/10.2478/auseme-2020-0001
Keywords
© 2020 Riazul Islam et al., published by Sciendo
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.
Dynamic logic circuits are widely popular due to a smaller number of transistors and consume less area. But the time to switch between logics is higher due to higher contention value. A new model of the logic using nMOS based keeper circuit is proposed and the performance is evaluated using Cadence tools. Comparative results demonstrate the suitability and competency of the proposed circuit.