5 ps Jitter Programmable Time Interval/Frequency Generator

Open access

Abstract

A new time interval/frequency generator with a jitter below 5 ps is described. The time interval generation mechanism is based on a phase shifting method with the use of a precise DDS synthesizer. The output pulses are produced in a Spartan-6 FPGA device, manufactured by Xilinx in 45 nm CMOS technology. Thorough tests of the phase shifting in a selected synthesizer are performed. The time interval resolution as low as 0.3 ps is achieved. However, the final resolution is limited to 500 ps to maximize precision. The designed device can be used as a source of high precision reference time intervals or a highly stable square wave signal of frequency up to 50 MHz.

[1] Rivoir, J., (2006). Full-digital time-to-digital converter for ATE with autonomous calibration. Proc. of IEEE Int. Test. Conf. 2006, Santa Clara, CA, USA, 1–10.

[2] Szplet, R., Jachna, Z., Kwiatkowski, P., Różyc. K. (2013). A 2.9 ps equivalent resolution interpolating time counter based on multiple coding lines. Meas. Sci. Technol., 24(3), 035904/1−15.

[3] Vornicu, I., Carmona-Galan, R., Rodriguez-Vazquez, A. (2016). Time interval generator with 8 ps resolution and wide range for large TDC array characterization. Analog. Integr. Cir. Sig. Process, 87(2), 181−189.

[4] Using Digitally Programmable Delay Generators. AN-260 Application Note, Analog Devices. http://www.analog.com/media/en/technical-documentation/application-notes/105895411AN-260.pdf. (1998).

[5] Alhdab, S., Mantyniemi, A., Kostamovaara, J. (2012). A 12-bit Digital-to-Time Converter (DTC) with sub-ps-level resolution using current DAC and differential switch for Time-to-Digital Converter (TDC). Proc. of IEEE I2MTC 2012., Graz, Austria, 2668−2671.

[6] Klepacki, K., Pawłowski, M., Szplet, R. (2015). Low-jitter wide-range integrated time interval/delay generator based on combination of period counting and capacitor charging. Rev. Sci. Instrum., 86(2), 025111/1−7.

[7] Rahkonen, T., Kostamovaara, J. (1993). The use of stabilized CMOS delay line for the digitization of short time intervals. IEEE J. Solid-State Circuits, 28(8), 887−894.

[8] Suchenek, M. (2009). Picosecond resolution programmable delay line. Meas. Sci. Technol., 20(11), 117005/1−5.

[9] Abdulrazzaq, B.I., Abdul Halin, I., Kawahito, S., Sidek, R.M., Shafie, S. Yunus, N.A.M. (2016). A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance. SpringerPlus, 5(1), 1−32.

[10] Huang, H.-Y., Shen, J.-H. (2004). A DLL-based programmable clock generator using threshold-trigger delay element and circular edge combiner. Proc. of IEEE AP ASIC 2004, Fukuoka, Japan, 76−79.

[11] Okayasu, T., Suda, M., Yamamoto, K., Kantake, S., Sudou, S., Watanabe, D. (2006). 1.83ps-resolution CMOS dynamic arbitrary timing generator for > 4 GHz ATE applications. Proc. of IEEE ISSCC 2006, San Francisco, CA, United States, 522−511.

[12] Carbone, P., Kiaei, S., Xu, F. (2014). Design, modelling and testing of data converters. Berlin, Germany: Springer-Verlag, ch. 7.

[13] Kwiatkowski, P., Jachna, Z., Różyc, K., Kalisz, J. (2012). Accurate and low jitter time-interval generators based on phase shifting method. Rev. Sci. Instrum., 83(3), 034701/1−4.

[14] Suchenek, M., Starecki, T. (2012). Programmable pulse generator based on programmable logic and direct digital synthesis. Rev. Sci. Instrum., 83(12), 124704/1−4.

[15] Chen, Y.-Y., Huang, J.-L., Kuo, T., Huang, X.-L. (2015). Design and implementation of an FPGA-based data/timing formatter. J. Electron. Test., 31(5−6), 549−559.

[16] Yao, Y., Wang, Z., Lu, H., Chen, L., Jin, G. (2016). Design of time interval generator based on hybrid counting method. Nucl. Instrum. Methods Phys. Res., Sect. A, 832, 103−107.

[17] Kalisz, J., Poniecki, A., Różyc, K. (2003). A simple, precise, and low jitter delay/gate generator. Rev. Sci. Instrum., 74(7), 3507−3509.

[18] Chen, P., Chen, P.-Y., Lai, J.-S., Chen, Y.-J. (2010). FPGA vernier digital-to-time converter with 1.58 ps resolution and 59.3 minutes operation range. IEEE Trans. Circuits Syst. I, Reg. Papers, 57(6), 1134−1142.

[19] Song, Y., Liang, H., Zhou, L., Du, J., Ma, J., Yue, Z. (2011). Large dynamic range high resolution digital delay generator based on FPGA. Proc. of ICECC 2011, Zhejiang, China, 2116−2118.

[20] Miari, L., Antonioli, S., Labanca, I., Crotti, M., Rech, I., Ghioni, M. (2015). Eight-channel fully adjustable pulse generator. IEEE Trans. Instrum. Meas., 64(9), 2399−2408.

[21] Kwiatkowski, P., Szplet, R., Jachna, Z., Różyc, K. (2016). A time digitizer based on multiphase clock implemented in FPGA device. Proc. of EBCCSP 2016, Cracow, Poland.

[22] Optimizing clock synthesis in small cells and heterogeneous networks. White Paper, Silicon Laboratories. https://www.silabs.com/Support%20Documents/TechnicalDocs/Silicon%20Labs%20Next-Generation%20DSPLL%20Technology%20White%20Paper%20-%20June%202015.pdf. (Jun. 2015)

[23] 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer. Datasheet, Analog Devices. http://www.analog.com/media/en/technical-documentation/data-sheets/AD9910.pdf. (May 2012).

[24] ISE In-Depth Tutorial. User Guide UG695, v.14.1, Xilinx. http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ise_tutorial_ug695.pdf. (Apr. 2012).

[25] Keysight Technologies Infiniium 90000 Series Oscilloscopes. Datasheet, Keysight Technologies. http://literature.cdn.keysight.com/litweb/pdf/5989-7819EN.pdf. (2015).

[26] Szplet, R., Kwiatkowski, P., Jachna, Z., Różyc, K. (2016). An eight-channel 4.5-ps precision timestamps-based time interval counter in FPGA chip, IEEE Trans. Instrum. Meas., 65(9), 2088−2100.

Metrology and Measurement Systems

The Journal of Committee on Metrology and Scientific Instrumentation of Polish Academy of Sciences

Journal Information


IMPACT FACTOR 2016: 1.598

CiteScore 2016: 1.58

SCImago Journal Rank (SJR) 2016: 0.460
Source Normalized Impact per Paper (SNIP) 2016: 1.228

Metrics

All Time Past Year Past 30 Days
Abstract Views 0 0 0
Full Text Views 133 133 22
PDF Downloads 56 56 9