The purpose of this work is to present the design flow and the implementation of a neuro-fuzzy controller Intellectual Property (IP) core, using High Level Synthesis (HLS) tool. The realized IP core is designed for FPGA based embedded system architectures. The implemented control algorithm is a Sugeno model based Adaptive Neuro-Fuzzy Inference System (ANFIS). The optimization possibilities using the HLS tool and the designing of the interfaces for the IP core are presented.
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