Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology

Abstract

This paper proposed a novel structure of a 10-bit, 400MS/s pipelined analog to digital convertor using 0.18 µm TSMC technology. In this paper, two stages are used to converter design and a new method is proposed to increase the speed of the pipeline analog to digital convertor. For this purpose, the amplifier is not used at the first stage and the buffer is used for data transfer to the second stage, in the second stage an amplifier circuit with accurate gain of 8 that is open loop with a new structure was used to speed up, also the design is such that the first 4 bits are extracted simultaneously with sampling. On the other hand, in this structure, since in the first stage the information is not amplified and transferred to the second stage, the accuracy of the comparator circuit should be high, therefore a new structure is proposed to design a comparator circuit that can detect unwanted offsets and eliminate them without delay, and thus can detect the smallest differences in input voltage. The proposed analog to digital convertor was designed with a resolution of 10 bits and a speed of 400MS/s, with the total power consumption 74.3mW using power supply of 1.8v.

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  • Abo, A.M., 1999. Design for reliability of low-voltage switched-capacitor circuits, Doctor of Philosophy in Electrical Engineering, University of California Berkeley.

  • Adimulam, M.K., Movva, K.K., Srinivas, M., 2017. A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications, 2017 30th IEEE International System-on-Chip Conference (SOCC), IEEE, pp. 45-50. doi: 10.1109/SOCC.2017.8226004.

  • Ali, A.M., Dinc, H., Bhoraskar, P., Dillon, C., Puckett, S., Gray, B., Speir, C., Lanford, J., Brunsilius, J., Derounian, P.R., 2014. A 14 Bit 1 GS/s RF sampling pipelined ADC with background calibration, IEEE Journal of Solid-State Circuits 49, pp. 2857-2867. doi: 10.1109/JSSC.2014.2361339.

  • Boo, H.H., Boning, D.S., Lee, H.-S., 2015. A 12b 250 MS/s pipelined ADC with virtual ground reference buffers, IEEE Journal of Solid-State Circuits 50, pp. 2912-2921, DOI: 10.1109/JSSC.2015.2467183.

  • Cárdenas-Olaya, A., Rubiola, E., Friedt, J.-M., Bourgeois, P.-Y., Ortolano, M., Micalizio, S., Calosso, C., 2017. Noise characterization of analog to digital converters for amplitude and phase noise measurements, Review of Scientific Instruments 88, p. 065108, DOI: 10.1063/1.4984948.

  • Correia, A.P.P., Barquinha, P.C., da Palma Goes, J.C., 2015. A Second-Order Σ∆ ADC Using Sputtered IGZO TFTs, Springer.

  • de Aguilar, J.D., Salinas, J., Lapuh, R., Méndez, A., Lagos, F.G., Sanmamed, Y., 2016. Characterization of the amplitude frequency response of analog-to-digital converters, 2016 Conference on Precision Electromagnetic Measurements (CPEM 2016), IEEE, pp. 1-2, DOI: 10.1109/CPEM.2016.7540455.

  • Fan, Q., Chen, J., Wen, X., Feng, Y., Tang, Y., Zuo, Z., Gong, D., Liu, T., Ye, J., 2017. A low-power 10-bit 250 MS/s dual-channel pipeline ADC in 0.18 μm CMOS, Journal of Instrumentation 12, p. C02018, DOI: 10.1088/1748-0221/12/02/C02018.

  • Fatemi-Behbahani, E., Farshidi, E., Ansari-Asl, K., 2016. Analysis of chaotic behavior in pipelined analog to digital converters, AEU-International Journal of Electronics and Communications 70, pp. 301-310, DOI: 10.1016/j.aeue.2015.12.008.

  • Holdsworth, B., Woods, C., 2002. Digital logic design, Elsevier.

  • Khalapure, S., Siddharth, R., Vasantha, M., 2017. Design of 5- Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, pp. 585-588, DOI: 10.1109/ISVLSI.2017.108.

  • Khorami, A., Sharifkhani, M., 2016. High-speed low-power comparator for analog to digital converters, AEU-International Journal of Electronics and Communications 70, pp. 886-894, DOI: 10.1142/S0218126617501183.

  • Kiran, K.R., Kumar, A., Reddy, A.S., Sarojini, M., 2016. A 5-bit, 0.08 mm 2 area flash analog to digital converter implemented on cadence virtuoso 180nm, 2016 International Conference on Emerging Trends in Engineering, Technology and Science (ICETETS), IEEE, pp. 1-6, DOI: 10.1109/ICETETS.2016.7603035.

  • Li, Y.F., Du, L., 2017. 1.5 bit-per-stage 8-bit Pipelined CMOS A/D Converter for Neuromophic Vision Processor, arXiv preprint arXiv:1701.08877.

  • Liu, C.-C., Chang, S.-J., Huang, G.-Y., Lin, Y.-Z., 2010. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure, IEEE Journal of Solid-State Circuits 45, pp. 731-740, DOI: 10.1109/JSSC.2010.2042254.

  • Liu, D., He, L., Lin, F., Li, T., Chou, Y.-K., 2017. A Time-Interleaved Statistically-Driven Two-Step Flash ADC for High-Speed Wireline Applications, Journal of Circuits, Systems and Computers 26, p. 1750118, DOI: 10.1142/S0218126617501183.

  • Lv, J., Que, L., Wei, L., Meng, Z., Zhou, Y., 2018. A low power and small area digital self-calibration technique for pipeline ADC, AEU-International Journal of Electronics and Communications 83, pp. 52-57, DOI: 10.1016/j.aeue.2017.08.025.

  • Murshed, A.M., Krishna, K.L., Saif, M.A., Anuradha, K., 2018. A 10-bit high speed pipelined ADC, 2018 2nd International Conference on Inventive Systems and Control (ICISC), IEEE, pp. 1253-1258, DOI: 10.1109/ICISC.2018.8399006.

  • Ozeki, T., Naka, J., Takuji, M., 2017. A/D converter including multiple sub-A/D converters, Google Patents.

  • Prakash, A.J., Jose, B.R., Mathew, J., Jose, B.A., 2017. A Differential Quantizer-Based Error Feedback Modulator for Analog-to-Digital Converters, IEEE Transactions on Circuits and Systems II: Express Briefs 65, pp. 21-25, DOI: 10.1109/TCSII.2017.2666822.

  • Rezapour, A., Tavakoli, M.B., Setoudeh, F., 2019. A new approach for 10-bit pipeline analog-to-digital converter design based on 0.18 µm CMOS technology, AEU-International Journal of Electronics and Communications 99, pp. 299-314, DOI: 10.1016/j.aeue.2018.10.030.

  • Rezapour, A., Tavakoli, M.B., Setoudeh, F., 2019. Analysis and design of a new structure for 10-bit 350MS/s pipeline analog-to-digital converter. Genero & Direito 8 - N. 03 – Ano, pp. 301-328, DOI: 10.22478/ufpb.2179-7137.2019v8n3.47576.

  • Roy, S., Banerjee, S., 2018. A 9-Bit 50 MSPS Quadrature Parallel Pipeline ADC for Communication Receiver Application, Journal of The Institution of Engineers (India): Series B 99, pp. 221-234, DOI: 10.1007/s40031-018-0315-y.

  • Sarkar, S., Cai, Y., Adak, A., 2017. Two-step residue transfer technique for high-speed pipeline A/Ds, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), IEEE, pp. 3-8, DOI: 10.1109/VLSID.2017.51.

  • Steensgaard-Madsen, J., 2016. Analog-to-digital converter, Google Patents.

  • Tao, S., 2015. Power-Efficient Continuous-Time Incremental Sigma-Delta Analog-to-Digital Converters, KTH Royal Institute of Technology, DOI: 10.1109/TCSI.2015.2418892.

  • Vyas, J.L., 2013. Simulation of 3 bit flash ADC in 0.18 µm technology using NG SPICE tool for high speed application, IJSRD. Int J Sci Res, Dev 1.

  • Wang, C., Wang, X., Ding, Y., Li, F., Wang, Z., 2018. A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, pp. 1-5, DOI: 10.1109/ISCAS.2018.8351100.

  • Wang, L., Meng, Q., Zhi, H., Li, F., 2017. A 10 bit 200 MS/s pipeline ADC using loading-balanced architecture in 0.18 μm CMOS, Journal of Semiconductors 38, p. 075003, DOI: 10.1088/1674-4926/38/7/075003.

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