Feasibility of FPGA to HPC computation migration of plasma impurities diagnostic algorithms

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Abstract

We present a feasibility study of fast events parameters estimation algorithms regarding their execution time. It is the first stage of procedure used on data gathered from gas electron multiplier (GEM) detector for diagnostic of plasma impurities. Measured execution times are estimates of achievable times for future and more complex algorithms. The work covers usage of Intel Xeon and Intel Xeon Phi - high-performance computing (HPC) devices as a possible replacement for FPGA with highlighted advantages and disadvantages. Results show that less than 10 ms feedback loop can be obtained with the usage of 25% hardware resources in Intel Xeon or 10% resources in Intel Xeon Phi which leaves space for future increase of algorithms complexity. Moreover, this work contains a simplified overview of basic problems in actual measurement systems for diagnostic of plasma impurities, and emerging trends in developed solutions.

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International Journal of Electronics and Telecommunications

The Journal of Committee of Electronics and Telecommunications of Polish Academy of Sciences

Journal Information


CiteScore 2016: 0.72

SCImago Journal Rank (SJR) 2016: 0.248
Source Normalized Impact per Paper (SNIP) 2016: 0.542

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