Hardware Accelerated Simulation of Crest Factor Reduction Block for Mobile Telecommunications

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This paper reports results of the hardware accelerated simulations of the crest factor reduction (CFR) block which is a common element of the radio signal processing path in base stations for mobile telecommunications. Presented approach increases productivity of radio system architects by shortening the time of model architecture evaluation. This enables unprecedented scale of CFR parameter optimization which requires thousands of simulation runs. We use FPGA device and Xilinx System Generator for DSP technology in order to model CFR block in MATLAB/Simulink environment, implement the accelerator and use it for mixed hardware-software simulation. Reported approach reduces simulation time by 70%, provides straightforward use of fixed-point arithmetic and lowers power consumption by 73% at the cost of constant and relatively low overhead on model development.

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International Journal of Electronics and Telecommunications

The Journal of Committee of Electronics and Telecommunications of Polish Academy of Sciences

Journal Information

CiteScore 2016: 0.72

SCImago Journal Rank (SJR) 2016: 0.248
Source Normalized Impact per Paper (SNIP) 2016: 0.542


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