Modeling the Arithmetic Decomposition of DA-LUT Block for Heterogeneous FPGA Structures

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Distributed arithmetic is well known technique of designing FIR filters in FPGA devices. The quality of such filter implementation strongly depends on synthesis results of the DALUT block. Heterogeneity of modern FPGA structures introduces new possibilities into implementation process, that may lead to better results, but also makes it more complicated. This paper presents the simple mathematical model for estimating the necessary FPGA resources to implement DA-LUT using decomposition-based approach. The model takes into account the type of logic cells or memory blocks used for decomposition process. The proposed model is helpful to determinate the DALUT decomposition strategy for further automation of modified distributed arithmetic decomposition method

[1] P. Longa, A. Miri, and M. Bolic, “A Flexible Design of Filterbank Architectures for Discrete Wavelet Transforms,” in Acoustics,Speech and Signal Processing, 2007. ICASSP 2007. IEEE InternationalConference on, vol. 3, Apr. 2007, pp. III-1441-III-1444, DOI: 10.1109/ICASSP.2007.367118.

[2] --, “Modified distributed arithmetic based architecture for discrete wavelet transforms,” Electronics Letters, vol. 44, no. 4, pp. 270-271, 2008, DOI: 10.1049/el:20082418.

[3] U. Meyer-Baese, J. Chen, C. H. Chang, and A. Dempster, “A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters,” in Circuits and Systems, 2006. APCCAS 2006.IEEE Asia Pacific Conference on, Dec. 2006, pp. 1555-1558, DOI: 10.1109/APCCAS.2006.342540.

[4] A. Dempster and M. Macleod, “Use of minimum-adder multiplier blocks in FIR digital filters,” Circuits and Systems II: Analog and Digital SignalProcessing, IEEE Transactions on, vol. 42, no. 9, pp. 569-577, Sep. 1995, DOI: 10.1109/82.466647.

[5] M. Martinez-Peiro, J. Valls, T. Sansaloni, A. Pascual, and E. Boemo, “A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation,” in Electronics, Circuits and Systems, 1999. Proceedings of ICECS ’99.The 6th IEEE International Conference on, vol. 1, 1999, pp. 241-244, DOI: 10.1109/ICECS.1999.812268.

[6] H. Yoo and D. Anderson, “Hardware-efficient distributed arithmetic architecture for high-order digital filters,” in Acoustics, Speech,and Signal Processing, 2005. Proceedings. (ICASSP ’05). IEEE InternationalConference on, vol. 5, Mar. 2005, pp. v/125-v/128, DOI: 10.1109/ICASSP.2005.1416256.

[7] P. Meher, S. Chandrasekaran, and A. Amira, “FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic,” Signal Processing, IEEE Transactions on, vol. 56, no. 7, pp. 3009-3017, Jul. 2008, DOI: 10.1109/TSP.2007.914926.

[8] T. Sasao, Y. Iguchi, and T. Suzuki, “On LUT cascade realizations of FIR filters,” in Digital System Design, 2005. Proceedings. 8th EuromicroConference on, Sep. 2005, pp. 467-474, DOI: 10.1109/DSD.2005.82.

[9] T. Sasao, “Analysis and synthesis of weighted-sum functions,” Computer-Aided Design of Integrated Circuits and Systems, IEEETransactions on, vol. 25, no. 5, pp. 789-796, May 2006, DOI: 10.1109/TCAD.2006.870407.

[10] M. Rawski, P. Tomaszewicz, H. Selvaraj, and T. Łuba, “Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures,” in Proceedings of the8th Euromicro Conference on Digital System Design, ser. DSD ’05. Washington, DC, USA: IEEE Computer Society, 2005, pp. 460-466, DOI: 10.1109/DSD.2005.81.

[11] M. Rawski, “Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAs,” InternationalJournal of Electronics and Telecommunications, vol. 56, no. 4, pp. 345-350, Nov. 2010, DOI: 10.2478/v10177-010-0045-. [Online]. Available:

[12] M. Staworko and M. Rawski, “Application of Modified Distributed Arithmetic Concept in FIR Filter Implementations Targeted at Heterogeneous FPGAs,” Przegla˛d Elektrotechniczny (Electrical Review), vol. 88, no. 6, pp. 240-246, Jun. 2012.

[13] Altera. (2011, May) FIR Compiler User Guide. Altera Corporation.

[14] J. He and J. Rose, “Advantages of heterogeneous logic block architecture for FPGAs,” in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, May 1993, pp. 7.4.1-7.4.5, DOI: 10.1109/CICC.1993.590578.

[15] J. Cong and S. Xu, “Delay-optimal technology mapping for FPGAs with heterogeneous LUTs,” in Design Automation Conference, 1998.Proceedings, Jun. 1998, pp. 704-707.

[16] I. Kuon, R. Tessier, and J. Rose, “FPGA Architecture: Survey and Challenges,” Found. Trends Electron. Des. Autom., vol. 2, no. 2, pp. 135-253, Feb. 2008, DOI: 10.1561/1000000005.

[17] I. Kuon and J. Rose, “Measuring the Gap Between FPGAs and ASICs,” Computer-Aided Design of Integrated Circuits and Systems,IEEE Transactions on, vol. 26, no. 2, pp. 203-215, Feb. 2007, DOI: 10.1109/TCAD.2006.884574.

[18] J. Rose, R. Francis, D. Lewis, and P. Chow, “Architecture of fieldprogrammable gate arrays: the effect of logic block functionality on area efficiency,” Solid-State Circuits, IEEE Journal of, vol. 25, no. 5, pp. 1217-1225, Oct. 1990, DOI: 10.1109/4.62145.

[19] E. Ahmed and J. Rose, “The effect of LUT and cluster size on deep-submicron FPGA performance and density,” Very Large ScaleIntegration (VLSI) Systems, IEEE Transactions on, vol. 12, no. 3, pp. 288-298, Mar. 2004, DOI: 10.1109/TVLSI.2004.824300.

[20] D. Lewis, E. Ahmed, G. Baeckler, V. Betz, M. Bourgeault, D. Cashman, D. Galloway, M. Hutton, C. Lane, A. Lee, P. Leventis, S. Marquardt, C. McClintock, K. Padalia, B. Pedersen, G. Powell, B. Ratchev, S. Reddy, J. Schleicher, K. Stevens, R. Yuan, R. Cliff, and J. Rose, “The Stratix II logic and routing architecture,” in Proceedings of the 2005ACM/SIGDA 13th international symposium on Field-programmable gatearrays, ser. FPGA ’05. New York, NY, USA: ACM, 2005, pp. 14-20, DOI: 10.1145/1046192.1046195.

[21] Altera. (2005, Aug.) Stratix II vs. Virtex-4 Density Comparison. Altera Corporation.

[22] --. (2005, Aug.) Stratix II vs. Virtex-4 Performance Comparison. Altera Corporation.

[23] H. Wong, V. Betz, and J. Rose, “Comparing FPGA vs. custom cmos and the impact on processor microarchitecture,” in Proceedings of the19th ACM/SIGDA international symposium on Field programmable gatearrays, ser. FPGA ’11. New York, NY, USA: ACM, 2011, pp. 5-14, DOI: 10.1145/1950413.1950419.

[24] J. Cong and S. Xu, “Technology mapping for FPGAs with embedded memory blocks,” in Proceedings of the 1998 ACM/SIGDAsixth international symposium on Field programmable gate arrays, ser. FPGA ’98. New York, NY, USA: ACM, 1998, pp. 179-188, DOI: 10.1145/275107.275138.

[25] S. Wilton, “Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays,” Computer-Aided Design ofIntegrated Circuits and Systems, IEEE Transactions on, vol. 19, no. 1, pp. 56-68, Jan. 2000, DOI: 10.1109/43.822620.

[26] G. Borowik, T. Łuba, and B. J. Falkowski, “Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories,” in DDECS, 2009, pp. 230-233, DOI: 10.1109/DDECS.2009.5012135.

[27] G. Borowik, “Improved State Encoding for FSM Implementation in FPGA Structures with Embedded Memory Blocks,” Electronics andTelecommunications Quarterly, vol. 54, pp. 9-28, Mar. 2008.

[28] M. Rawski, T. Łuba, and B. J. Falkowski, “Logic synthesis method for FPGAs with embedded memory blocks,” in ISCAS. IEEE, May 2008, pp. 2014-2017, DOI: 10.1109/ISCAS.2008.4541842.

[29] M. Rawski, G. Borowik, T. Łuba, P. Tomaszewicz, and B. Falkowski, “Logic synthesis strategy for fpgas with embedded memory blocks,” in Mixed Design of Integrated Circuits Systems, 2009. MIXDES ’09.MIXDES-16th International Conference, Jun. 2009, pp. 296-301.

[30] Altera, “Stratix III Device Handbook,” Altera Corporation, Mar. 2011.

[31] Xilinx, “Virtex-5 FPGA User Guide,” Xilinx Inc., p. 385, Mar. 2012.

[32] --, “Virtex-6 FPGA Configurable Logic Block User Guide,” Xilinx Inc., p. 385, Mar. 2012.

[33] --, “Virtex-6 FPGA Memory Resources User Guide,” Xilinx Inc., p. 385, Apr. 2011.

[34] U. Meyer-Baese, Digital Signal Processing with Field ProgrammableGate Arrays, 3rd ed. Springer Publishing Company, Incorporated, 2007.

[35] M. J. Beauchamp, S. Hauck, K. D. Underwood, and K. S. Hemmert, “Embedded floating-point units in FPGAs,” in Proceedings of the 2006ACM/SIGDA 14th international symposium on Field programmable gatearrays, ser. FPGA ’06. New York, NY, USA: ACM, 2006, pp. 12-20, DOI: 10.1145/1117201.1117204.

International Journal of Electronics and Telecommunications

The Journal of Committee of Electronics and Telecommunications of Polish Academy of Sciences

Journal Information

CiteScore 2016: 0.72

SCImago Journal Rank (SJR) 2016: 0.248
Source Normalized Impact per Paper (SNIP) 2016: 0.542


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