Dual synthesis of Petri net based application specific logic controllers with increased safety

Open access


In the paper, design flow of the application specific logic controllers with increased safety by means of Petri nets is proposed. The controller architecture is based on duplicated control unit and comparison results from both units. One specification of control algorithm is used by means of Petri net for both units. The hardware duplication is obtained during dual synthesis process. This process uses two different logic synthesis methods to obtain two different hardware configurations for both control units. Additionally, the dual verification is applied to increase reliability of the control algorithm. Such design flow simplifies the process of realization of control systems with increased safety.

[1] K. Biliński, M. Adamski, J. Saul, and E. Dagless, “Petri-net-based algorithms for parallel-controller synthesis”, IEEE Proceedings – Computers and Digital Techniques 141 (6), 405–412 (1994).

[2] C. Girault and R. Valk, Petri Nets for System Engineering: A Guide to Modeling, Verification, and Applications Springer-Verlag, Berlin/Heidelberg (2003).

[3] A. Khamis, D. Zydek, G. Borowik, and D. S. Naidu, “Control system design based on modern embedded systems”, Lecture Notes in Computer Science 8112, 491–498, Springer-Verlag, Berlin/Heidelberg (2013).

[4] R. Wiśniewski, A. Barkalov, L. Titarenko, and W. Halang, “Design of microprogrammed controllers to be implemented in FPGAs”, International Journal of Applied Mathematics and Computer Science 21 (2), 401–412 (2011).

[5] A. Milik and E. Hrynkiewicz, “On translation of LD, IL and SFC given according to IEC-61131 for hardware synthesis of reconfigurable controller”, Proceedings of the 19th IFAC World Congress, 4477–4483, IFAC (2014).

[6] J. Mocha and D. Kania, “Sprzętowa realizacja programu sterowania w strukturach FPGA”, Przegląd Elektrotechniczny 88 (12a), 95–100 (2012).

[7] A. Milik, “On ladder diagrams compilation and synthesis to FPGA implemented reconfigurable logic controller”, Advances in Electrical and Electronic Engineering 12 (5), 443–451 (2014).

[8] M. Rawski, P. Tomaszewicz, G. Borowik, and T. Łuba, “Logic synthesis method of digital circuits designed for implementation with embedded memory blocks of FPGAs”, Lecture Notes in Electrical Engineering 79, 121–144 (2011).

[9] N. Chang, W. H. Kwon, and J. Park, “Hardware implementation of real-time Petri-net-based controllers”, Control Engineering Practice 6 (7), 889–895 (1998).

[10] M. Węgrzyn, “Implementation of safety critical logic controller by means of FPGA”, Annual Reviews in Control 27 (1), 55–61 (2003).

[11] W. A. Halang, M. Śnieżek, and S.-K. Jung, “A real-time computing architecture for applications with high safety and predictability requirements”, 1st IEEE International Workshop on Real-Time Computing System and Applications RTCSA'94, 153–157, Seoul, South Korea (1994).

[12] W. A. Halang and M. Adamski, “A programmable electronic system for safety related control applications”, Advances in safety and reliability: Proceedings of the International Conference ESREL'97, 349–355, Oxford, Pergamon (1997).

[13] N. Marranghello, J. Mirkowski, and K. Bilinski, “Synthesis of synchronous digital systems specified by Petri nets” in A. Yakovlev, L. Gomes, and L. Lavagno (edts.), Hardware Design and Petri Nets, 129–150, Kluwer Academic Publishers, Boston (2000).

[14] T. Murata, “Petri nets: Properties, analysis and applications”, Proceedings of the IEEE 77(4), 541–580 (1989).

[15] M. Adamski and J. Tkacz, “Formal reasoning in logic design of reconfigurable controllers” in Proceedings of 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems, 1–6, Brno, Czech Rep. (2012).

[16] A. Bukowiec and M. Adamski, “Logic synthesis for FPGAs of interpreted Petri net with common operation memory”, 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems PDeS 2012, 57–62 (2012).

[17] A. Bukowiec and M. Adamski, “Synthesis of Petri nets into FPGA with operation flexible memories” in Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS'12, 16–21, Tallinn, Estonia (2012).

[18] G. Borowik, T. Łuba, and B. J. Falkowski, “Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories”, in 12th International Symposium on Design and Diagnostics of Electronic Circuits Systems 2009, 230–233 (2009).

[19] A. Bukowiec and M. Węgrzyn, “Design of safety critical logic controller using devices integrated microprocessor with FPGA”, Proceedings of SPIE 5775, 377–384 (2005).

[20] A. Karatkevich, “Dynamic analysis of Petri net-based discrete systems”, Lecture Notes in Control and Information Sciences 356 (2007).

[21] T. Kozłowski, E. Dagless, J. Saul, M. Adamski, and J. Szajna, “Parallel controller synthesis using Petri nets”, IEEE Proceedings – Computers and Digital Techniques, 142 (4), 263–271 (1995).

[22] K. Jensen, K. Kristensen, and L. Wells, “Coloured Petri nets and CPN tools for modelling and validation of concurrent systems”, International Journal on Software Tools for Technology Transfer 9 (3), 213–254 (2007).

[23] V. Savi and X. Xie, “Liveness and boundedness analysis for petri nets with event graph modules”, Lecture Notes in Computer Science 616, 328–347 (1992).

[24] M. Sałamaj, “Conception of a control unit for critical systems”, International Journal of Electronics and Telecommunications 59 (4), 363–368 (2013).

[25] J. Tkacz, “State machine type colouring of Petri net by means of using a symbolic deduction method”, Measurement Automation and Monitoring 53 (5), 120–122 (2007).

[26] M. Doligalski, “Behavioral specification of the logic controllers by means of the hierarchical configurable Petri nets”, Proceedings of 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems, 80–83, Brno (2012).

[27] H. Foster, A. Krolnik, and D. Lacey, Assertion-Based Design, Kluwer Academic Publishers, Norwell (2004).

Bulletin of the Polish Academy of Sciences Technical Sciences

The Journal of Polish Academy of Sciences

Journal Information

IMPACT FACTOR 2016: 1.156
5-year IMPACT FACTOR: 1.238

CiteScore 2016: 1.50

SCImago Journal Rank (SJR) 2016: 0.457
Source Normalized Impact per Paper (SNIP) 2016: 1.239


All Time Past Year Past 30 Days
Abstract Views 0 0 0
Full Text Views 191 152 11
PDF Downloads 60 51 5