In this paper, the digital algorithm and the device for the demodulation of the quadrature amplitude modulation signals are considered. The fundamental advantages of our approach are simple hardware implementation, minimal number of arithmetic operations required over the signal period as well as the potential interference immunity in the presence of Gaussian noise. The expressions have been found for the error probability and their inaccuracy has been estimated. By means of the statistical simulation methods, the practical interference immunity of the introduced demodulator, together with the influence of phase locking errors have been tested. The introduced demodulator can be implemented either as a device independent from the programmable logic devices, or as an installation unit of the receiver equipment.