In modern computing technique, calculation of leading zeros in a data represented as strings of digits is used very often. Those techniques require high speed of the circuit, as well as its fast design. In this paper we propose a design of such a counter, which is applicable to data length of w = 4j bits, for 4 < j ≤ 8. With this solution it is also possible to process longer data, since the suggested technique offers a good modularity. This is very important, considering the current technology scaling trends. In this paper, a delay behavior of the proposed circuit has also been investigated using equations and VHDL simulation based worst-case delay estimation method. The results show a significant improvement of the circuit speed, compared to the known solutions.