Parallel implementation of local thresholding in Mitrion-C
Mitrion-C based implementations of three image processing algorithms: a look-up table operation, simple local thresholding and Sauvola's local thresholding are described. Implementation results, performance of the design and FPGA logic utilization are discussed.
CONTEXT ADAPTIVE VARIABLE LENGTH CODING (CAVLC) is a method designed for coding residual pixel data after transform and quantization, in which different codes with variable length are chosen based on recently coded coefficients. Coded bitstream can be stored or transmitted. This method is optional in widely adopted H.264 video coding standard. The entire algorithm is a complex one, and also difficult to implement efficiently in Field-Programmable Gate Array (FPGA), due to data dependency. When the complexity of the Register Transfer Logic (RTL) implementation rises, it impacts the duration and costs of development. Therefore, usage of High Level Synthesis (HLS) may be beneficial with these types of projects. In this paper first known to authors implementation of CAVLC and Exp-Golomb decoders for H.264 intra decoder in Impulse C language will be presented and compared with other implementations. Proposed solution is able to decode more then 720p@40fps with FPGA module clock at 166MHz.
Decision trees and decision tree ensembles are popular machine learning methods, used for classification and regression. In this paper, an FPGA implementation of decision trees and tree ensembles for letter and digit recognition in Vivado High-Level Synthesis is presented. Two publicly available datasets were used at both training and testing stages. Different optimizations for tree code and tree node layout in memory are considered. Classification accuracy, throughput and resource usage for different training algorithms, tree depths and ensemble sizes are discussed. The correctness of the module’s operation was verified using C/RTL cosimulation and on a Zynq-7000 SoC device, using Xillybus IP core for data transfer between the processing system and the programmable logic.
In this paper an embedded vision system for human silhouette detection in thermal images is presented. As the computing platform a reprogrammable device (FPGA – Field Programmable Gate Array) is used. The detection algorithm is based on a sliding window approach, which content is compared with a probabilistic template. Moreover, detection is four scales in supported. On the used test database, the proposed method obtained 97% accuracy, with average one false detection per frame. Due to the used parallelization and pipelining real-time processing for 720 × 480 @ 50 fps and 1280 × 720 @ 50 fps video streams was achieved. The system has been practically verified in a test setup with a thermal camera.
The article describes research on dishes segmentation for the purposes of customer service process automation in a self-service canteen. The project assumptions and a prototype test stand are presented. The developed empty workspace detection and tray position determination algorithms are discussed. Finally, the chosen dishes segmentation algorithm is described and justified.