Search Results

You are looking at 1 - 3 of 3 items for

  • Author: M. Reaz x
Clear All Modify Search
Open access

M. Hasan and M. Reaz

Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction

The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.

Open access

Q. Yousef, M. B. I. Reaz and M. A. M. Ali

This study presents the variations of photoplethysmogram (PPG) morphology with age. PPG measurement is done noninvasively at the index finger on both right and left hands for a sample of erectile dysfunction (ED) subjects. Some parameters are derived from the analysis of PPG contour showed in association with age. The age is found to be an important factor that affects the contour of PPG signals which accelerates the disappearance of PPG’s dicrotic notch and PPG’s inflection point as well. Arterial compliance is found to be degraded with age due to the fall of arterial elasticity. This study approaches the establishment of usefulness of PPG’s contour analysis as an investigator to the changes in the elastic properties of the vascular system, and as a detector of early sub-clinical atherosclerosis.

Open access

M. Arif Sobhan Bhuiyan, M. Bin Ibne Reaz, J. Jalil and L. Farzana Rahman

Abstract

This paper proposes a transmit/receive (T/R) nanoswitch in 130 nm CMOS technology for 2.4 GHz ISM band transceivers. It exhibits 1.03-dB insertion loss, 27.57-dB isolation and a power handling capacity (P1 dB) of 36.2-dBm. It dissipates only 6.87 μW power for 1.8/0 V control voltages and is capable of switching in 416.61 ps. Besides insertion loss and isolation of the nanoswitch is found to vary by 0.1 dB and 0.9 dB, respectively for a temperature change of 125°C. Only the transistor W/L optimization and resistive body floating technique is used for such lucrative performances. Besides absence of bulky inductors and capacitors in the schematic circuit help to attain the smallest chip area of 0.0071 mm2 which is the lowest ever reported in this frequency band. Therefore, simplicity and low chip area of the circuit trim down the cost of fabrication without compromising the performance issue.