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Open access

W. Jendernalik, J. Jakusz, G. Blakiewicz, R. Piotrowski and S. Szczepański

CMOS realisation of analogue processor for early vision processing

The architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms is presented. The proof-of-concept prototype vision chip containing 32 × 32 photosensor array and 32 analogue processors is fabricated using a 0.35 μm CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 frames per second, or achieve very low power consumption, several μW. Finally, the experimental results are presented and discussed.

Open access

G. Blakiewicz, J. Jakusz, W. Jendernalik and S. Szczepański

Abstract

In this paper, a tuning method of a resonant circuit suited for wireless powering of miniature endoscopic capsules is presented and discussed. The method allows for an automatic tuning of the resonant frequency and matching impedance of a full wave rectifier loading the resonant circuit. Thereby, the receiver tunes so as to obtain the highest power efficiency under given conditions of transmission. A prototype receiver for wireless power reception, fabricated in in AMS CMOS 0.35 μm technology, was used to verify correct operation of the proposed tuning. The prototype system produces a stable supply voltage, adjustable in the range of 1.2–1.8 V at a maximum output current of 100–67 mA, which is sufficient to power a typical endoscopic capsule.

Open access

W. Jendernalik, J. Jakusz, G. Blakiewicz and S. Szczepański

Abstract

An analogue median filter, realised in a 0.35 μm CMOS technology, is presented in this paper. The key advantages of the filter are: high speed of image processing (50 frames per second), low-power operation (below 1.25 mW under 3.3 V supply) and relatively high accuracy of signal processing. The presented filter is a part of an integrated circuit for image processing (a vision chip), containing: a photo-sensor matrix, a set of analogue pre-processors, and interface circuits. The analysis of the main parameters of the considered median filter is presented. The discussion of important limitations in the operation of the filter due to the restrictions imposed by CMOS technology is also presented.