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S. Szczepański, M. Wöjcikowski, B. Pankiewicz, M. KŁosowski and R. Żaglewski

FPGA and ASIC implementation of the algorithm for traffic monitoring in urban areas

This paper describes the idea and the implementation of the image detection algorithm, that can be used in integrated sensor networks for environment and traffic monitoring in urban areas. The algorithm is dedicated to the extraction of moving vehicles from real-time camera images for the evaluation of traffic parameters, such as the number of vehicles, their direction of movement and their approximate speed. The authors, apart from the careful selection of particular steps of the algorithm towards hardware implementation, also proposed novel improvements, resulting in increasing the robustness and the efficiency. A single, stationary, monochrome camera is used, simple shadow and highlight elimination is performed. The occlusions are not taken into account, due to placing the camera at a location high above the road. The algorithm is designed and implemented in pipelined hardware, therefore high frame-rate efficiency has been achieved. The algorithm has been implemented and tested in FPGA and ASIC.

Open access

B. Pankiewicz

Abstract

In this paper the multiple output current amplifier basic cell is proposed. The triple output current mirror and current follower circuit are described in detail. The cell consists of a split nMOS differential pair and accompanying biasing current sources. It is suitable for low voltage operation and exhibits highly linear DC response. Through cell devices scaling, not only unity, but also any current gains are achievable. As examples, a current amplifier and bandpass biquad section designed in CMOS TSMC 90nm technology are presented. The current amplifier is powered from a 1.2V supply. MOS transistors scaling was chosen to obtain output gains equal to -2, 1 and 2. Simulated real gains are -1.941, 0.966 and 1.932 respectively. The 3dB passband obtained is above 20MHz, while current consumption is independent of input and output currents and is only 7.77μA. The bandpass biquad section utilises the previously presented amplifier, two capacitors and one resistor, and has a Q factor equal to 4 and pole frequency equal to 100 kHz.

Open access

B. Pankiewicz, S. Szczepański and M. Wójcikowski

Abstract

In this paper, the MOS differential pair driven simultaneously from gates and bulk terminals is described. An approximated analytical solution of the voltage to current transfer function has been found for the proposed circuit. Four possible combinations of gate and bulk connections of the input signal are presented. Basing on the configuration giving the best linearity, the operational transconductance amplifier (OTA) has been designed and compared, by computer simulations, to the amplifier utilizing the gate driven classic MOS pair. 3rd order filters using the OTAs with linearized and simple MOS pair have been designed and the resulting parameters have been compared. Linearization through the presented simultaneous use of gate and bulk terminals seems to be useful for low voltage applications.