In this paper a new structure of digital clock recovery — DCR circuit is presented. The main features of this DCR are: low complexity design, low power consumption and a single system clock operation. Thus, multiple instantiation of this type of DCR on a single chip is not complex. Due to this, such DCR can target application in energy-efficient cognitive radio systems with carrier aggregation. For performance evaluation, we have derived Markov chain based mathematical model for peak-to-peak and root mean square jitter performance analysis. The stability problem of this model, rising from the fact that some phase error states have several orders of magnitude lower probabilities than the others, is solved using mathematical apparatus for symbolic analysis. The mathematical model validity is examined by laboratorial measurements of proposed DCR for 4-PAM signal. The measurement methodology and results are described in details.
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