Test Procedures for Synchronized Oscillators Network CMOS VLSI Chip

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Abstract

The paper presents test procedures designed for application-specific integrated circuit (ASIC) CMOS VLSI chip prototype that implements a synchronized oscillator neural network with a matrix size of 32×32 for object detecting in binary images. Networks of synchronized oscillators are recently developed tool for image segmentation and analysis. This paper briefly introduces synchronized oscillators network. Basic chip analog building blocks with their test procedures and measurements results are presented. In order to do measurements, special basic building blocks test structures have been implemented in the chip. It let compare Spectre simulations results to measurements results. Moreover, basic chip analog building blocks measurements give precious information about their imperfections caused by MOS transistor mismatch. This information is very usable during design and improvement of a special setup for chip functional tests. Improvement of the setup is a digitally assisted analog technique. It is an original idea of oscillators tuning procedure used during chip prototype testing. Such setup, oscillators tuning procedure and segmentation of sample binary images are presented

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International Journal of Electronics and Telecommunications

The Journal of Committee of Electronics and Telecommunications of Polish Academy of Sciences

Journal Information


CiteScore 2016: 0.72

SCImago Journal Rank (SJR) 2016: 0.248
Source Normalized Impact per Paper (SNIP) 2016: 0.542

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