CMOS realisation of analogue processor for early vision processing

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CMOS realisation of analogue processor for early vision processing

The architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms is presented. The proof-of-concept prototype vision chip containing 32 × 32 photosensor array and 32 analogue processors is fabricated using a 0.35 μm CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 frames per second, or achieve very low power consumption, several μW. Finally, the experimental results are presented and discussed.

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Bulletin of the Polish Academy of Sciences Technical Sciences

The Journal of Polish Academy of Sciences

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IMPACT FACTOR 2016: 1.156
5-year IMPACT FACTOR: 1.238

CiteScore 2016: 1.50

SCImago Journal Rank (SJR) 2016: 0.457
Source Normalized Impact per Paper (SNIP) 2016: 1.239


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